1. Field of the Invention
This invention relates to an insulated gate transistor (IGT) having a PN-junction region in a drain region of a MOS field effect transistor using a semiconductor substrate as the drain region and, more particularly, to an improvement which is operable at a low drain-source voltage (VDS).
2. Description of the Related Art
As a high-power device, a vertical MOS field effect transistor has been widely used wherein a source region of one conductivity type is formed in a base region of the other conductivity type, which in turn is formed in a semiconductor substrate of the one conductivity type, as a drain region. A gate electrode is formed on the base region located between the source and drain regions, via a gate insulator film. This kind of vertical MOS field effect transistor enables a drain current to flow across the thickness of the semiconductor substrate, thus allowing a large power consumption. This vertical MOS field effect transistor, however, has a drawback since it has a large ON-resistance due to the current flow across the thickness of the substrate which causes a large power loss.
For solving the problem of this large ON-resistance, an IGT has been proposed by M. F. Chang et al in IEDM83, pages 83 to 86. The IGT has a high impurity region of the other conductivity type in the drain region which is in contact with the drain electrode to interpose the other conductivity type region between the drain region and the drain electrode. According to this IGT, a charge carrier injection of other conductivity type carriers is generated from the high impurity region to the drain region as a reaction to the drain current flowing into the high impurity region. By the carrier injection, a conductivity modulation is generated to make the ON-resistance very small.
The injected charge carriers are, however, majority carriers of the high impurity region. Therefore, the PN-junction between the drain region and the high impurity region is necessarily forwardly biased. This required forward bias restricts the lower limit of the drain-source voltage to more than 0 5 or 0.6 volts. In a region of the drain-source voltage which is lower than this value, there is only a little drain current, thus losing the transistor action. Thus, the proposed IGT has a drawback that it does not operate in a low drain-source voltage.
The proposed IGT has another drawback since there is a deterioration of the operating speed. When the IGT turns off, a discharging path does not exist for the charges in the drain region due to the existance of the high impurity region. Therefore, the IGT does not turn off until the charges in the drain region disappear by recombination in the drain region.
As an IGT which is operable at a low drain-source voltage and with a high speed, a lateral IGT has been proposed, by M. R. Simpson in IEDM85, pages 740 to 743. In this lateral IGT, the high impurity region is formed in the same surface of the drain region in which the base and source regions are formed. The drain electrode is connected with the high impurity, region and a portion of the drain region located on the opposite side of the high impurity region to the source and drain regions. Drain current flows laterally along the surface of the drain region.
In a high drain-source voltage region, the PN-junction between the high impurity region and the drain region is forwardly biased to allow the carrier injection. The resistance component of the drain region under the high impurity region restricts the drain current following directly to the drain electrode, thus resulting in the IGT operation. On the other hand, in a low drain-source voltage region, since the IGT operation does not function due to an insufficient forward bias of the PN-junction between the high impurity region and the drain region, the drain current bypasses the high impurity region to flow directly to the drain electrode resulting in a MOS field effect transistor action. Thus, the lateral IGT can operate in a low drain-source voltage region. Furthermore, if the lateral IGT turns off, the carriers remaining in the drain region can be discharged through the direct connection of the drain region and the drain electrode. Therefore, the lateral IGT can operate at a high speed.
This lateral IGT, however, has a large ON-resistance based on a drain current flowing along the surface of the drain region. For the same reason, this IGT requires a large area on a semiconductor chip to increase the current capacity.
Another improvement of the IGT has been proposed by T. Goto et al in a Japanese Laid-open Patent Application No. 60-170263 published on Sept. 3, 1985. This improved IGT has the high impurity region of a lattice shape or a comb shape in a bottom region of the drain region. This improvement gives an improved high speed operation, a low ON-resistance and a large current capacity. It is, however, difficult to obtain a sufficient resistance component in the drain region positioned adjacent to the high impurity region. Due to this insufficient resistance component, the MOS field effect transistor normally operates up to a large drain-field source voltage. The low ON-resistance cannot be obtained until the drain-source becomes fairly high voltage.